Computer Architecture and Microprocessor – Multiple Choice Questions (MCQ) With Answers

computer microprocessor MCQ Answers techhyme

A Digital computer can be considered as a digital system that performs various computational tasks. The first electronic digital computer was developed in the late 1940s and was used primarily for numerical computations. By convention, the digital computers use the binary number system, which has two digits: 0 and 1. A binary digit is called a bit.

A computer system is subdivided into two functional entities: Hardware and Software

Also Read: Cisco Enterprise Wireless Networks – Multiple Choice Questions With Answers

The hardware consists of all the electronic components and electromechanical devices that comprise the physical entity of the device. The software of the computer consists of the instructions and data that the computer manipulates to perform various data-processing tasks. Computer Organization is realization of what is specified by the computer architecture. It deals with how operational attributes are linked together to meet the requirements specified by computer architecture. Some organizational attributes are hardware details, control signals and peripherals.

Below is the list of most common MCQ Questions related to Computer Architecture and Microprocessor

1. In computers, subtraction is generally carried out by ?

(a) 9’s complement
(b) 10’s complement
(c) 1’s complement
(d) 2’s complement
(e) None of these

Correct Answer: (d)

2. The number of bus controllers that are used for interfacing of memory and I/O devices is?

(a) 1
(b) 2
(c) 3
(d) None of the mentioned
(e) 5

Correct Answer: (b)

3. If MBYTES input is high, then the pin serves as?

(a) AEN
(b) CEN
(c) AEN and CEN
(d) None of the mentioned
(e) GEN

Correct Answer: (a)

4.What characteristic of RAM memory makes it not suitable for permanent storage?

(a) too slow
(b) unreliable
(c) it is volatile
(d) too bulky
(e) None of these

Correct Answer: (c)

5. The average time required to reach a storage location in memory and obtain its contents is called the?

(a) seek time
(b) turnaround time
(c) access time
(d) transfer time
(e) None of these

Correct Answer: (c)

6. Which of the following is not a weighted code?

(a) Decimal Number system
(b) Excess 3-cod
(c) Binary number System
(d) Machine number system
(e) None of these

Correct Answer: (b)

7. In the application where all the interrupting devices are of equal priority, the mode used is?

(a) automatic rotation
(b) automatic EOI mode
(c) specific rotation
(d) EOI
(e) None of these

Correct Answer: (a)

8. In cascaded mode, the number of vectored interrupts provided by 8259A is?

(a) 4
(b) 8
(c) 16
(d) 64
(e) None of these

Correct Answer: (d)

9. The circuit used to store one bit of data is known as?

(a) Register
(b) Encoder
(c) Decoder
(d) Flip Flop
(e) None of these

Correct Answer: (d)

10. The pin that requests the access of the system bus is?

(a) HLDA
(b) HRQ
(c) ADSTB
(d) none of the mentioned
(e) CEN

Correct Answer: (b)

11. In a memory-mapped I/O system, which of the following will not be there?

(a) LDA
(b) IN
(c)ADD
(d) OUT
(e) None of these

Correct Answer: (a)

12. The number of hardware interrupts that the processor 8085 consists of is?

(a) 1
(b) 3
(c) 5
(d) 7
(e) None of these

Correct Answer: (c)

13. Write Through technique is used in which memory updating the data?

(a) Virtual memory
(b) Main memory
(c) Auxiliary memory
(d) Cache memory
(e) None of these

Correct Answer: (d)

14.Generally Dynamic RAM is used as main memory computer system as it?

(a) Consumes less power
(b) has higher speed
(c) has lower cell density
(d) needs refreshing circuitry
(e) None of these

Correct Answer: (b)

15. The 8257 is able to accomplish the operation of?

(a) verifying DMA operation
(b) write operation
(c) read operation
(d) all of the mentioned
(e) Only (b) and (c)

Correct Answer: (d)

16. Virtual memory consists of?

(a) Static RAM
(b) Dynamic RAM
(c) Magnetic memory
(d) Cache memory
(e) None of these

Correct Answer: (a)

17. A Stack-organised Computer uses instruction of?

(a) Indirect addressing
(b) Two-addressing
(c) Zero addressing
(d) Index addressing
(e) None of these

Correct Answer: (c)

18. The bus is available when the DMA controller receives the signal?

(a) HRQ
(b) HLDA
(c) DACK
(d) all of the mentioned
(e) None of these

Correct Answer: (b)

19. The register of 8257 that can only be written in is?

(a) DMA address register
(b) terminal count register
(c) mode set register
(d) status register
(e) None of these

Correct Answer: (c)

20. An n-bit microprocessor has?

(a) n-bit program counter
(b) n-bit address register
(c) n-bit ALU
(d) n-bit instruction register
(e) None of these

Correct Answer: (d)

21. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when

(a) auto load is set
(b) auto load is reset
(c) TC STOP bit is reset
(d) TC STOP bit is set
(e) None of these

Correct Answer: (d)

22. The multlplicand register & multiplier register of a hardware circuit implementing booth’s algorithm have (11101) & (1100). The result shall be

(a) (812) 10
(b) (-12) 10
(c) (12) 10
(d) (-812) 10
(e) None of these

Correct Answer: (a)

23. PSW is saved in stack when there is a

(a) interrupt recognised
(b) execution of RST instruction
(c) Execution of CALL instruction
(d) All of these
(e) None of these

Correct Answer: (a)

24. The IOW (active low) in its slave mode loads the contents of data bus to

(a) 8-bit mode register
(b) upper/lower byte of 16-bit DMA address register
(c) terminal count register
(d) all of the mentioned
(e) None of these

Correct Answer: (d)

25. A k-bit field can specify any one of

(a) 3k registers
(b) 2k registers
(c) K2 registers
(d) K3 registers
(e) None of these

Correct Answer: (b)

26. In reading the columns of a keyboard matrix, when no key is pressed then all the pins show

(a) 0
(b)1
(c) F
(d) 7
(e) None of these

Correct Answer: (b)

27. The instructions which copy information from one location to another either in the processor’s internal register set or in the external main memory are called

(a) Data transfer instructions.
(b) Program control instructions.
(c) Input-output instructions.
(d] Logical instructions.
(e) None of these

Correct Answer: (a)

28. What are the actual steps that are followed in identifying any key that is being pressed?

(a) wait for the debounce time
(b) identify the key that is pressed
(c) initially no key should be pressed
(d) all of the mentioned
(e) None of these

Correct Answer: (d)

29. Memory access in RISC architecture is limited to instructions

(a) CALL and RET
(b) PUSH and POP
(c) STA and LDA
(d) MOV and JMP
(e) None of these

Correct Answer: (c)

30. To identify that the key is present in which row and the column

(a) we ground the bits of the row one by one
(b) we ground the bits of the column one by one
(c) we connect the bits of the row to the logic level 1 one by one
(d) we can connect the columns to the logic level 1 one by one
(e) None of these

Correct Answer: (a)

31. PC Program Counter is also call ……………………………

(a) instruction pointer
(b) memory pointer
(c) data counter
(d) file pointer
(e) None of these

Correct Answer: (a)

32. The registers that store the keyboard and display modes and operations programmed by CPU are

(a) I/O control and data buffers
(b) control and timing registers
(c) return buffers
(d) display address registers
(e) None of these

Correct Answer: (b)

33. CPU does not perform the operation …………….?

(a) data transfer
(b) logic operation
(c) arithmetic operation
(d) all of the above
(e) None of these

Correct Answer: (a)

34. The access time of memory is …………….. the time required for performing any single CPU operation.

(a) Longer than
(b) Shorter than
(c) Negligible than
(d) Same as
(e) None of these

Correct Answer: (a)

35. The sensor RAM acts as 8-byte first-in-first-out RAM in

(a) keyboard mode
(b) strobed input mode
(c) keyboard and strobed input mode
(d) scanned sensor matrix mode
(e) None of these

Correct Answer: (c)

36. The data that is entered from the left side of the display unit is of

(a) left entry mode
(b) right entry mode
(c) left and right entry modes
(d) Upper entry mode
(e) None of these

Correct Answer: (a)

37. Data hazards occur when ………………

(a) Greater performance loss
(b) Pipeline changes the order of read/write access to operands
(c) Some functional unit is not fully pipelined
(d) Machine size is limited
(e) None of these

Correct Answer: (b)

38. Which of the following is not a mode of data transmission?

(a) simplex
(b) duplex
(c) semi duplex
(d) half duplex
(e) None of these

Correct Answer: (c)

39. Interrupts which are initiated by an instruction are

(a) internal
(b) external
(c) hardware
(d) software
(e) None of these

Correct Answer: (d)

40. TXD (Transmitted Data Output) pin carries serial stream of the transmitted data bits along with

(a) start bit
(b) stop bit
(c) parity bit
(d) all of the mentioned
(e) None of these

Correct Answer: (d)

41. In 8257 (DMA), each of the four channels has

(a) a pair of two 8-bit registers
(b) a pair of two 16-bit registers
(c) one 16-bit register
(d) one 8-bit register
(e) None of these

Correct Answer: (b)

42. Logic gates with a set of input and outputs is arrangement of

(a) Computational circuit
(b) Logic circuit
(c) Design circuits
(d) Register
(e) None of these

Correct Answer: (a)

43. A micro program sequencer

(a) generates the address of next micro instruction to be executed.
(b) generates the control signals to execute a microinstruction.
(c) sequentially averages all microinstructions in the control memory.
(d) enables the efficient handling of a micro program subroutine.
(e) None of these

Correct Answer: (a)

44. The common register(s) for all the four channels of 8257 are

(a) DMA address register
(b) terminal count register
(c) mode set register and status register
(d) none of the mentioned
(e)Both (a) and (b)

Correct Answer: (c)

45. In Reverse Polish notation, expression A*B+C*D is written as

(a) AB*CD*+
(b) A*BCD*+
(c) AB*CD+*
(d) A*B*CD+
(e) None of these

Correct Answer: (a)

46. Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer stayed the same what would the bandwidth of the bus?

(a) 1 Megabyte/sec
(b) 4 Megabytes/sec
(c) 8 Megabytes/sec
(d) 2 Megabytes/sec
(e) None of these

Correct Answer: (d)

47. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

(a) the time its takes for the platter to make a MI rotation
(b) the time it takes for the read-write head to move into position over the appropriate track
(c) the time it takes for the platter to rotate the correct sector under the head
(d) none of the above
(e) All of the above

Correct Answer: (a)

48. The IOR (active low) input line acts as output in

(a) slave mode
(b) master mode
(c) master and slave mode
(d) none of the mentioned
(e) All of the mentioned

Correct Answer: (b)

49. Computers use addressing mode techniques for

(a) giving programming versatility to the user by providing facilities as pointers to memory counters for loop control
(b) to reduce no. of bits in the field of instruction
(c) specifying rules for modifying or interpreting address field of the instruction
(d) All the above
(e) None of these

Correct Answer: (d)

50. The pin that disables all the DMA channels by clearing the mode registers is

(a) MARK
(b) CLEAR
(c) RESET
(d) READY
(e) None of these

Correct Answer: (c)

51 . (2FAOC) 16 is equivalent to

(a) (195 084) 10
(b) (001011111010 0000 1100) 2
(c) Both (a) and (b)
(d) (194 085)10
(e) None of these

Correct Answer: (b)

52. The pin that is used to write data to the addressed memory location, during DMA write operation is

(a) MEMR (active low)
(b) AEN
(c) MEMW (active low)
(d) IOW (active low)
(e) None of these

Correct Answer: (c)

53. The register that stores all the interrupt requests in it in order to serve them one by one on

(a) Interrupt Request Register
(b) In-Service Register
(c) Priority resolver
(d) Interrupt Mask Register
(e) None of these

Correct Answer: (a)

54. If memory access takes 20 ns with cache and 110 ns without it, then the ratio (cache uses a 10 ns memory) is

(a) 93%
(b) 90%
(c) 88%
(d) 87%
(e) None of these

Correct Answer: (b)

55. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be

(a) 11 bits
(c) 16 bits
(e) None of these
(b) 21 bits
(d) 20 bits

Correct Answer: (c)

56. Flip Flop can be converted into T-Flip Flop by using additional logic circuit

(a) n TQD =
(b) T D =
(c) D = T . Q n
(d) n TQD =?
(e) None of these

Correct Answer: (d)

57. Once the ICW1 is loaded, then the initialization procedure involves

(a) edge sense circuit is reset
(b) IMR is cleared
(c) slave mode address is set to 7
(d) all of the mentioned
(e) None of these

Correct Answer: (d)

58. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch and data bus cycles is

(a) COD
(b) INTA (active low)
(c) M/10 (active low)
(d) all of the mentioned
(e) None of these

Correct Answer: (d)

59. ‘Aging registers’ are

(a) Counters which indicate how long ago their associated pages have been referenced.
(b) Registers which keep track of when the program was last accessed.
(c) Counters to keep track of last accessed instruction.
(d) Counters to keep track of the latest data structures referred.
(e) None of these

Correct Answer: (a)

60. SIMD represents an organization that

(a) refers to a computer system capable of processing several programs at the same time.
(b) represents organization of single computer containing a control unit, processor unit and a memory unit.
(c) includes many processing units under the supervision of a common control unit
(d) none of the above.
(e) All (a), (b) and (c)

Correct Answer: (c)